Virtually all logic circuits using metal-semiconductor field-effect transistors (MESFETs) or heterojunction field-effect transistors (HFETs), referred to herein as simply FETs, operate at relatively low power supply voltages to minimize power dissipation. For FET logic circuits constructed using Gallium Arsenide (GaAs) technology, the power supply voltage is typically two volts. This choice of supply voltage results from the logic signal inputs to the logic circuits having a limited voltage range, or swing, due to input voltage clamping by the FETs, as will be demonstrated below. It is understood that the input voltage clamping by the FETs is an inherent result of the structure of the FETs themselves; a Schottky barrier is formed at the junction of the gate and channel portion (disposed between the source and drain) of the FET, allowing current to flow into the gate should the gate voltage exceed the Schottky barrier height, an exemplary 0.7 volts for "enhancement" type FETs and 1.5 volts for "depletion" type FETs. The terminology of "enhancement" and "depletion" FETs refers to the operation of the FET at zero gate-to-source voltage: an "enhancement" type FET is off (substantially no current flowing from source to drain) with zero bias and a "depletion" type FET is on (near maximum current flow between source and drain) at zero bias. It is understood that logic circuits utilizing insulated-gate FETs do not suffer from input voltage clamping of the type discussed here. However, insulated gate FETs, such as metal-oxide-semiconductor FETs available in silicon technology, are not readily manufacturable in GaAs technology. A detailed description of the electrical characteristics of MESFETs in logic circuits and selectively doped HFETs are discussed in "Gallium Arsenide Technology," edited by D. K. Ferry, 1985, pp. 331-341 and 119-125, respectively.
It is noted that the terminology logical "zero" and logical "one" are used to denote the logical state of signals, usually defined as being below and above a predetermined voltage, respectively. The predetermined voltage is typically referred to as the switching voltage of the logic circuits used: the switching voltage is the input voltage to the logic circuit at which the output thereof changes logic state. Further, the designation V.sub.SS and V.sub.DD are used to identify a power source as well as the voltage supplied by the power source and will be used interchangeably.
One consequence of using low power supply voltages for logic circuits is the limited difference in output voltage of the logic circuits between a logical "one" output or a logical "zero" output and the switching voltage of subsequent logic circuits, commonly known as the logical "one" and logical "zero" noise margins, respectively. The smaller either of the noise margins become, the greater the likelihood of electrical noise changing the logic state of a signal. This problem is compounded in integrated circuits where many hundreds, or thousands, of logic circuits are changing state, generating the electrical noise in close proximity to one another. Still further, as will be discussed in greater detail below, the reduced power supply voltage restricts the logic functions which can be performed by the logic circuit to be the inclusive "OR" or "NOR" function.
As stated above, the logic input voltage range is set by the FETs coupling to the logic inputs of the logic circuit, clamping the input voltage to typically one or two times the Schottky barrier height voltage. Referring to FIG. 4, the logic circuit 400 shown is known in the art as direct-coupled FET logic, or DCFL. With the FETs 401, 402 as shown, the logic input IN has a voltage range of essentially V.sub.SS (typically 0 volts or ground) plus the on voltage of FET 401 from a preceding logic circuit (as will be explained in more detail below), an exemplary 0.1 volts, to the barrier height voltage of the enhancement type FET 401, an exemplary 0.7 volts. Beyond 0.7 volts, the current into the gate of FET 401 becomes excessive. The switching voltage is slightly above the threshold voltage of FET 401 which, for purposes here, makes the switching voltage an exemplary 0.25 volts. As stated above, the logic voltage range, or swing, for a DCFL circuit 400 is essentially 0.1 to 0.7 volts. This makes the noise margin for a logical "zero" to be 0.25-0.1 volts, or 150 mV, whereas for a logical "one", the noise margin is 0.7-0.25 volts, or 450 mV. Depletion type FET 402 acts as a passive load for FET 401, pulling up the output OUT to V.sub.DD, typically two volts, when FET 401 is off, and no load is coupled to the output OUT. Hence the output voltage of the circuit 400 can range from V.sub.DD to 0.1 volts whereas the input to the logic circuit 400 limits the voltage swing independently of the power supply voltage V.sub.DD. Therefore the voltage V.sub.DD is limited to as low a voltage as practical to reduce the power dissipation of the DCFL circuit 400.
Although not shown here, logical functions, such as the inclusive "OR" function, can be provided by having another FET in parallel with the FET 401 except for the gate terminal. However, to provide a logical "AND" function within the logic circuit 400 alone, i.e., not by using multiple logic circuits 400 to synthesize the logical "AND" function using De Morgan's theorem, another FET (not shown) must be disposed in series between FET 401 and the output OUT. The resulting circuit would require both FETs to be on for the output to change. For both FETs to be on, a logical "one" must be applied to the gates of both FETs. This is not practical, however, since the logical "one" voltage for one FET will be different than for the other FET since they are in series, i.e., the logical "one" for FET 401 is limited to 0.7 volts while the logical "one" voltage for the other FET is 0.7 volts above the drain-to-source voltage of FET 401 when it is on, here 0.8 volts. Therefore, the noise margin for the logic signal to the other FET will be less than the noise margin for the logic signal to FET 401 if the logic swing is limited to 0.7 volts by another logic circuit 400. In addition, the logical "zero" output voltage of the logic circuit having a logical "AND" capability is increased with each FET in series with FET 401, reducing the noise margin for logical "zero". Using the above exemplary FET on voltages and switching voltage, the noise margin is 0.25 volts less the on voltages of the two FETs in series, resulting in a noise margin of 50 mV, instead of the 150 mV as before. Given the present manufacturing capability of FETs in GaAs, a wide variation in the threshold voltage of FET 401 can occur across the wafer, as well as within a single chip, resulting in the switching voltage of the logic circuit 400 being so varied that the logical "zero" noise margin can effectively go to zero. Hence, reliable complex logic networks using multiple DCFL logic circuits is difficult, if not impossible, to achieve in practice when there is electrical noise present.
To overcome these limitations, another logic family, called source-follower field-effect logic (SFFL), was invented by A. I. Faris and P. J. Robertson and disclosed in a patent application filed 23 August 1988, serial No. 07/235,862, and assigned to the same assignee as this invention. An exemplary embodiment thereof is shown in FIG. 5. As shown, FETs 501 and 502 correspond to FETs 401, 402 in FIG. 4. However, the FETs 503-505 form the input stage to the logic circuit 500 and complex logic functions, such as inclusive "OR", are performed by parallel-connecting multiple FETs 503, similar to that done with FET 401 in FIG. 4. Here the switching voltage is an exemplary 1 volt and the maximum input voltage is two times the barrier height voltage (FETs 501 and 503), or an exemplary 1.4 volts, yielding a considerably larger noise margin for the logical "zero" logic level. As in the DCFL circuit 400 (FIG. 4), the output voltage swing can be from V.sub.DD to approximately 0.1 volts. Still the output voltage swings are limited by the input of the logic circuit 500 to the exemplary 1.4 volts. Hence, the voltage V.sub.DD is reduced to minimize power dissipation as in the case for DCFL. A typical voltage for V.sub.DD is 2 volts.
As given above, neither logic circuit types, DCFL (FIG. 4) or SFFL (FIG. 5), have power supply voltages and switching voltages that are compatible with popular logic types commonly used throughout industry, e.g., transistor-transistor logic (TTL) or complementary-metal-oxide-semiconductor logic (CMOS). TTL has a worst-case switching voltage of approximately 1.4 volts and operates from a substantially 5 volt power supply. CMOS logic can, in some cases, operate from 3 volts to 15 volts, and have a switching voltage of approximately one-half the power supply voltage. Typically CMOS logic circuits operate at 5 volts resulting in a switching voltage of approximately 2.5 volts. For the DCFL or SFFL circuits to operate in combination with TTL or CMOS, special voltage translators are required, which slows down the performance of the DCFL or SFFL and dissipates power. Further, at least two power supplies are required: 5 volts for the TTL or CMOS logic and 2 volts for the SFFL or DCFL.